dc.contributor.author | Melton, Roy | |
dc.contributor.author | Huang, Tsai | |
dc.contributor.author | Wills, Linda | |
dc.contributor.author | Alford, Cecil | |
dc.date.accessioned | 2008-10-21T13:52:50Z | |
dc.date.available | 2008-10-21T13:52:50Z | |
dc.date.issued | 2005-11 | |
dc.identifier.citation | Huang, T., Melton, R., Wills, L., Alford, C., "Predicting communication protocol performance on superscalar architectures using instruction dependency," Performance Evaluation, (2005). | en_US |
dc.identifier.uri | http://hdl.handle.net/1850/7261 | |
dc.description | RIT community members may access full-text via RIT Libraries licensed databases: http://library.rit.edu/databases/ | |
dc.description.abstract | Increasing diversity in telecommunication workloads leads to greater complexity in communication protocols. This occurs as
channel bandwidth rapidly increases. These factors result in larger computational loads for network processors that are increasingly
turning to high performance microprocessor designs. This paper presents an analytical method for estimating the performance of
instruction level parallel (ILP) processors executing network protocol processing applications. Instruction dependency information
extracted while executing an application is used to calculate upper and lower bounds for throughput, measured in instructions per
cycle (IPC). Results using UDP/TCP/IP applications show that the simulated IPC values fall between the analytically derived upper
and lower bounds, validating the model. The analytical method is much less expensive than cycle-accurate simulation, but reveals
similar throughput performance predictions. This allows the architectural design space for network superscalar processors to be
explored more rapidly and comprehensively, to reveal the maximum IPC that is possible for a given application workload and the
available hardware resources. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | Elsevier Science | en_US |
dc.subject | Network processing | en_US |
dc.subject | Analytical performance modeling | en_US |
dc.subject | Instruction dependency | en_US |
dc.title | Predicting communication protocol performance on superscalar architectures using instruction dependency | en_US |
dc.type | Postprint | en_US |
dc.identifier.url | http://dx.doi.org/10.1016/j.peva.2005.10.004 | |